1. Field of the Invention
This invention relates to data storage systems, and more particularly to data storage systems having a storage device controller interposed between a host computer and one or more data storage devices wherein the controller manages the storage of data within the one or more storage devices.
2. Description of the Related Art
Auxiliary storage devices such as magnetic or optical disk arrays are usually preferred for high-volume data storage. Many modern computer applications, such as high resolution video or graphic displays involving on-demand video servers, may heavily depend on the capacity of the host computer to perform in a data-intensive environment. In other words, necessity for external storage of data in relatively slower auxiliary data storage devices demands that the host computer system accomplish requisite data transfers at a rate that does not severely restrict the utility of the application that necessitated high-volume data transfers. Due to the speed differential between a host processor and an external storage device, a storage controller is almost invariably employed to manage data transfers to/from the host and from/to the storage device.
The purpose of a storage controller is to manage the storage for the host processor, leaving the higher speed host processor to perform other tasks during the time the storage controller accomplishes the requested data transfer to/from the external storage. The host generally performs simple data operations such as data reads and data writes. It is the duty of the storage controller to manage storage redundancy, hardware failure recovery, and volume organization for the data in the auxiliary storage. Redundant array of independent disks (RAID) algorithms are often used to manage data storage among a number of disk drives.
FIG. 1 is a diagram of a conventional computer system 10 including a host computer 12 coupled to a storage controller 14 by an interconnect link 16, and two storage devices 18A-18B coupled to storage controller 14 by respective interconnect links 20A and 20B. Each storage device 18 may be, for example, a disk drive array or a tape drive. Links 16 and 20A-20B may include suitable interfaces for I/O data transfers (e.g., Fibre Channel, small computer system interface or SCSI, etc.) As evident in FIG. 1, all of the information involved in data transfers between host computer 12 and storage devices 18A-18B passes through storage controller 14. Storage controller 14 receives command, status, and data packets during the data transfer.
FIG. 2 is a diagram illustrating an exemplary flow of control and data packets during a data read operation initiated by host computer 12 of FIG. 1. Links 16 and 20A-20B in FIG. 1 may be Fibre Channel links, and the data transfer protocol of FIGS. 1 and 2 may be the Fibre Channel protocol. Referring to FIGS. 1 and 2 together, host computer 12 issues a read command packet identifying storage controller 14 as its destination (XID=H,A) via link 16. Storage controller 14 receives the read command and determines that two separate read operations are required to obtain the requested data; one from storage device 18A and the other from storage device 18B.
Storage controller 14 translates the read command from host computer 12 into two separate read commands, one read command for storage device 18A and the other read command for storage device 18B. Storage controller 14 transmits a first read command packet identifying storage device 18A as its destination (XID=A,B) via link 20A, and a second read command packet identifying storage device 18B as its destination (XID=A,C) via link 20B. Each read command packet instructs respective storage devices 18A-18B to access and provide data identified by the read command. Storage device 18A (ID=B) accesses the requested data and transmits a data packet followed by a status packet (XID=B,A) to storage controller 14 via link 20A. Storage device 18B (ID=C) accesses the requested data and transmits a data packet followed by a status packet (XID=C,A) to storage controller 14 via link 20B. Each status packet may indicate whether the corresponding read operation was successful (i.e. whether the data read was valid).
Storage controller 14 typically includes a memory unit, and temporarily stores data and status packets in the memory unit. Storage controller 14 then consolidates the data received from storage devices 18A-18B and processes the status packets received from storage devices 18A-18B to form a composite status. Storage controller 14 transmits the consolidated data followed by the composite status (XID=A,H) to host computer 12 via link 16, completing the read operation. In the event that the composite status indicates a read operation error, host computer 12 may ignore the consolidated data and initiate a new read operation. In general, the flow of packets depicted in FIG. 2 is typical of a two-party point-to-point interface protocol (e.g., the Fibre Channel protocol).
As indicated in FIG. 1, storage controller 14 includes multiple communication ports. In addition to the memory and the multiple communication ports, storage controller 14 also typically includes one or more central processing units (CPUs). The multiple communication ports and the CPUs may be coupled to a communication bus. The CPUs and the memory may be coupled to a common bus within storage controller 14, and the CPUs may access the memory via the bus.
Two parameters are commonly used to measure the performance of a storage system: (1) the number of input/output (I/O) operations per second (IOPS), and (2) the data transfer rate of the storage system. Generally, the rate of execution of I/O operations by a storage controller is governed by the type, speed and number of CPUs within the storage controller. The data transfer rate depends on the data transfer bandwidth of the storage controller. In computer system 10 described above, all of the data transferred between host computer 12 and storage devices 18A-18B is temporarily stored within the memory of storage controller 14, and thus travels through the bus of storage controller 14. As a result, the data transfer bandwidth of storage controller 14 is largely dependent upon the bandwidth of the bus of storage controller 14.
Current storage systems have restricted scalability because of the storage controllers having a relatively inflexible ratio of CPU to bandwidth capability. This is especially true if they are based on xe2x80x9coff-the-shelfxe2x80x9d microprocessors or computer systems. Usually the storage controller is designed to satisfy the majority of IOPS and data rate performance requirements with one implementation. This interdependence between IOPS and data transfer rate results in less efficient scalability of performance parameters. For example, in conventional storage controller architectures, an increase in data transfer rate may require both an increase in data transfer bandwidth and an increase in the number of CPUs residing within the controller.
It would thus be desirable to have a storage controller where control functionality (as measured by the IOPS parameter) is scalable independently of the data transfer bandwidth (which determines the data transfer rate), and vice versa. It may be further desirable to achieve independence in scalability without necessitating a change in the existing interface protocol managing the host-controller-storage interface.
One embodiment of a storage controller is described including a controller memory, one or more central processing units (CPUs), and a host bus adapter all coupled to a controller bus. The one or more CPUs are configured to produce data routing information dependent upon a data transfer command which directs a transfer of data between a host computer and one or more storage devices. The host bus adapter includes a receive unit and a transmit unit adapted for coupling to a transmission medium. The host bus adapter receives the data routing information, and forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory. As a result, the data transfer mechanism does not rely upon availability of the controller bus and/or the one or more CPUs, allowing independent scalability of input/output operations per second (IOPS) and data transfer rate of a storage system including the storage controller. Embodiments of storage and computer systems including the storage controller are also described.
The storage controller may receive the data transfer command via the receive unit of the host bus adapter, and may store the data transfer command within the controller memory. The controller memory may also store configuration information of the one or more storage devices. The configuration information may include, for example, redundant array of independent disks (RAID) configuration information of the one or more storage devices. The one or more CPUs may access the data transfer command and the configuration information within the controller memory in order to: (i) translate the data transfer command dependent upon the configuration information of the one or more storage devices, thereby producing one or more translated data transfer commands, and (ii) produce the data routing information. The one or more CPUs may forward the one or more translated data transfer commands to the host bus adapter, and the host bus adapter may transmit the one or more translated data transfer commands upon the transmission medium via the transmit unit.
The host bus adapter may store the data routing information within a host bus adapter memory. In one embodiment, the host bus adapter memory includes a first lookup table and a data buffer area, and the data routing information includes command identification information one or more pointers to different data buffers within the data buffer area. The command identification information uniquely identifies the data transfer command. The command identification information and the one or more pointers are stored within the first lookup table. The host bus adapter stores the data associated with the data transfer command within the data buffers using the pointers. When all of the data associated with the data transfer command has been received by the host bus adapter, the host bus adapter forwards the data associated with the data transfer command from the host bus adapter memory to the transmit unit, and the transmit unit transmits the data upon the transmission medium. As a result, the host bus adapter forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory.
In an alternate embodiment, the host bus adapter memory includes a second lookup table, and the data routing information includes target header information and corresponding substitute header information. The target header information includes at least a portion of a header field of an expected data frame, and the substitute header information includes header information to be substituted by the receive unit for the header information of the expected data frame. The target header information and the corresponding substitute header information are stored within the second lookup table. The host bus adapter compares header information of a received data frame to the target header information within the lookup table. If the header information of the received data frame matches the target header information, the host bus adapter replaces the header information of the received data frame with the substitute header information corresponding to the target header information, and forwards the received data frame from the receive unit to the transmit unit. The transmit unit transmits the received data frame upon the transmission medium. As a result, the host bus adapter forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory.
One embodiment of a storage system is described including one or more storage devices coupled to the storage controller described above. The one or more storage devices may include multiple disk drives, the storage controller may manage the one or more storage devices as a RAID array, and the configuration information of the one or more storage devices may include RAID array configuration information of the one or more storage devices. The one or more CPUs translate the data transfer command as described above, producing the one or more translated data transfer commands. The host bus adapter transmits the one or more translated data transfer commands to the one or more storage devices (e.g., via the transmit unit and a transmission medium).
The one or more CPUs also produce data routing information dependent upon the data transfer command and the configuration information of the one or more storage devices. The host bus adapter receives the data routing information and stores the data routing information within the host bus adapter memory. The host bus adapter forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information and independent of the controller bus and the controller memory (i.e., such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory).
One embodiment of a computer system includes a host computer, the one or more storage devices, a transmission medium coupled to the host computer and to the one or more storage devices, and the storage controller described above, wherein the receive and transmit units of the host bus adapter of the storage controller are coupled to the transmission medium. As described above, the host bus adapter forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information and independent of the controller bus and the controller memory.
One method for conveying data within a storage system includes providing a storage controller comprising a host bus adapter and a controller memory coupled to a controller bus, wherein the host bus adapter comprises a receive unit, a transmit unit, and a host bus adapter memory. The receive and transmit units of the host bus adapter are coupled to a host computer and at least one storage device. A data transfer command is received from the host computer. Data routing information is generated within the storage controller dependent upon the data transfer command and stored within the host bus adapter memory. Data associated with the data transfer command is forwarded from the receive unit to the transmit unit of the host bus adapter dependent upon the data routing information and independent of the controller bus and the controller memory.
A second method for conveying data is intended for use in a storage system including a storage controller having a command processor (e.g., multiple CPUs), and a host adapter coupled to a controller bus. The method includes the host adapter receiving a data transfer command from a host computer coupled to the host adapter. The host adapter conveys the data transfer command to the command processor via the controller bus. The command processor generates data routing information dependent upon the data transfer command, and conveys the data routing information to the host adapter via the controller bus. The host adapter receives data for the data transfer command from one or more storage devices, and forwards the data to the host computer such that the data is conveyed from the one or more storage devices to the host computer without being conveyed on the controller bus or to the command processor.
A third method for conveying data is intended for use within the storage system described above. The host adapter receives a data transfer command from a host computer coupled to the host adapter. The host adapter conveys the data transfer command to the command processor via the controller bus. The command processor translates the data transfer command into one or more device data transfer commands, and conveys the device data transfer commands to the host adapter via the controller bus. The host adapter forwards the device data transfer commands to one or more storage devices. The host adapter receives data in response to the device data transfer commands and forwards the data to the host computer such that the data is conveyed from the one or more storage devices to the host computer without being conveyed on the controller bus or to the command processor.